This U.S. nonprovisional application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2003-33048 filed May 23, 2003, the contents of which are incorporated by reference in its entirety.
Arbitration mechanisms for improving bus bandwidth between at least one master and at least one target slave are known. The basic operation of such an arbitration includes a request, arbitration, grant, and data transfer.
When an arbiter grants bus ownership to a master, who requested access to a target slave, but the slave is unavailable to accommodate the data transfer, the result is a wasted grant of ownership, because the master must wait until the target slave is available for the data transfer. When the master accesses a target slave having long latency, the bandwidth is also degraded.
FIG. 1 illustrates a conventional timing diagram, which illustrates a waiting time T. As shown in FIG. 1, a first set of address information ADDR1-4 is supplied, followed by a first set of data DATA D1-D4. Subsequently, a second set of address information ADDR5-8 is supplied, followed by a second set of data DATA D5-D8. As shown in FIG. 1, the waiting time T is a delay between the availability of data DATA D4 and D5. This delay is undesirable. FIG. 2 illustrates a desirable timing diagram where the waiting time T is eliminated.
Bank interleaving has been used as a conventional technique to divide a memory into several banks, thereby permitting successive accesses to each bank. In bank interleaving, operations to each of the two banks is overlapped, for example, data is accessed in one bank and pre-charged in another bank simultaneously, in order to improve the bus bandwidth.
However, there are disadvantages with bank interleaving. In particular, only after the master receives bus ownership based on an arbitration, can the master drive the valid address and control information. Therefore, this information cannot be used for arbitration because the information is generated after the arbitration. As a result, bandwidth improvements are limited. Further, because the request to the target slave can not be sent in advance, a waiting time delay, such as T described above, still exists.
Other conventional devices include having a master generate a cycle type signal at the same time as a request. The cycle type signal indicates the specific target resource (slave) to be accessed and whether the target is to be read or written. Based on the cycle type signal and the related target resource information, the arbiter determines the priority of bus ownership. In this manner, a target slave retry cycle is avoided and bus bandwidth and overall system performance may be improved. However, additional pins are required to implement the cycle type signal and because the request to the target slave can not be sent in advance, the waiting time delay, such as T, still exists.
FIG. 3 illustrates a conventional bus architecture, including masters 1-3, an arbiter 4, an SDRAM controller 5, and an SDRAM bank 6. Each master 1-3 requests bus access from the arbiter 4, via an HBUSREQN signal. The arbiter 4, which includes arbitration logic for selecting one of the masters 1-3, performs arbitration and grants access to the bus via an HGRANTN signal, which is supplied to the selected one among the masters 1-3. As shown in FIG. 3, the HADDRN, HWRITEN, HBURSTN, HSIZEN, and HTRANN signals are each signals to drive a target slave. These signals are supplied from the masters 1-3 to the SDRAM controller 5 via one or more multiplexers (MUXs) 7-8. The MUXs 7-8 receive an HMASTER signal from the arbiter 4 and forward the selected HDDR, HWRITER, HBURSTR, HSIZER, and/or HTRANR to the SDRAM controller 5. MUX 7 receives an HWDATAN signal from each of the masters 1-3 and forwards the selected one among the HWDATAN signals as a BIWDATA signal to the SDRAM controller 5. The SDRAM controller 5, when ready, sends a BIREADYD signal to each of the masters 1-3. The SDRAM controller 5 also exchanges signals and data back and forth between the SDRAM 6.
FIG. 4 illustrates a timing diagram of a conventional bus architecture. As indicated in FIG. 4, a waiting time T exists between the transfer of the first data BODO-BOD3 and the second data B1D0-B1D3. This waiting time T reduces bus bandwidth efficiency and is caused by the fact the arbiter cannot request the target slave to prepare for data access prior to receiving the bus ownership through arbitration.